Semiconductor Device and Manufacturing Method Thereof

ABSTRACT

A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO 2  film continuously on the SiOCH film by reducing a carbon concentration therein in the chamber in which plasma is being generated, performing a plasma etching on the insulating film by using the SiOCH film and the SiO 2  film as a hardmask layer, to form a trench in the insulating film, and performing wet etching on a surface of the trench formed in the insulating film, to remove a layer damaged by the plasma etching and process residues.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2009-010266, filed Jan. 20, 2009,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and amanufacturing method thereof, and more specifically to an interconnecttechnology incorporating a low-k film, which is an interlayer insulatingfilm of a low relative dielectric constant.

2. Description of the Related Art

As the packing density of a semiconductor device is increased, the widthand thickness of interconnect layers become smaller, and the spacingbetween the interconnect layers becomes smaller. This increases signaldelay times. A delay time is determined by a parasitic resistance R anda parasitic capacitance C of interconnects. Basically, as theinterconnects become finer, both the parasitic resistance R and theparasitic capacitance C increase. The parasitic resistance R can bereduced by adopting a low-resistance material such as copper for aninterconnect material (Cu interconnects). On the other hand, theparasitic capacitance C decreases as the effective dielectric constantkeff of the interlayer insulating film deposited between theinterconnects is reduced. In other words, the parasitic capacitance Ccan be reduced by the interlayer insulating film having a lower relativedielectric constant k, and therefore an interlayer insulating filmhaving a low relative dielectric constant (k is 3.0 or less), called alow-k film, has been employed.

However, when interconnect trenches are formed in a low-k film by plasmatreatment (for hardmask layer formation and RIE), a reaction occursbetween oxygen utilized in the treatment and carbon. Due to thisreaction, carbon escapes from the low-k film, producing a “damagedlayer” on the surface of the low-k film (see, for example, Jeong-HoonAhn, “Integration of a low-k α-SiOC:H dielectric with Cu interconnects”,Journal of the Korean Physical Society (South Korea) Vol. 41, No. 4,October 2002, pp. 422-426; Gross, T. S., “Nanoscale observation ofdielectric damage to low k MSQ interconnects”, Materials, Technology andReliability of Advanced Interconnects—2005, Symposium (MaterialsResearch Society Proceedings, Vol. 863) xiii+411, pp. 165-169 2005; andBhanap. A, “Repairing process-induced damage to porous low-k ILDs bypost-ash treatment”, Advanced Metallization Conference 2003 xxiii+792pp. 519-523 2004). The damaged layer, which has a high relativedielectric constant, increases the capacitance between theinterconnects. Furthermore, because the damaged layer can easily absorbmoisture, the barrier metal and Cu interconnects tend to undergooxidation, which reduces the reliability of the interconnects. In orderto avoid such problems, the damaged layer is removed with a hydrofluoricacid solution after the interconnect trench formation. This wet etchingtreatment using the solution is performed also to remove processresidues on the lower interconnect at the bottom of the via. Withoutthis treatment, conduction defects would occur between the via and thelower interconnect.

However, the wet etching of the damaged layer proceeds more quickly thanthe etching of hardmask layer. For this reason, undercuts are created inthe low-k film beneath the hardmask layer HM (SiO₂ film in thisexample), as shown in FIGS. 1A and 1B (see the area [HM undercut]circled in FIG. 1B). The overhang portions formed by these undercutslead to defects caused by insufficient embedment of interconnect metalinto the interconnect trenches. Hence, the defects in the embedment mayoccur along the interconnect trenches as indicated by white streaks inFIG. 1C, and voids appear as indicated by blackened areas disturbing thepatterns in the lower left corner of the drawing.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising: forming aninsulating film of a material having a low relative dielectric constanton a substrate; forming a silicon oxycarbide (SiOCH) film on theinsulating film in a chamber; forming a silicon dioxide (SiO₂) filmcontinuously on the SiOCH film by reducing a carbon concentrationtherein in the chamber in which plasma is being generated; performing aplasma etching on the insulating film by using the SiOCH film and theSiO₂ film as a hardmask layer, to form a trench in the insulating film;and performing wet etching on a surface of the trench formed in theinsulating film, to remove a layer damaged by the plasma etching andprocess residues.

According to a second aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising: forming aSiOCH film on a substrate in a chamber; forming a SiO₂ film continuouslyon the SiOCH film by reducing a carbon concentration therein in thechamber in which plasma is being generated; performing a plasma etchingon the SiOCH film by using the SiO₂ film as a hardmask layer, to form atrench in the SiOCH film; and performing wet etching on a surface of thetrench formed in the SiOCH film, to remove a layer damaged by the plasmaetching and process residues.

According to a third aspect of the present invention, there is provideda method of manufacturing a semiconductor device, comprising: forming aSiOCH film on a substrate; forming, on the SiOCH film, a dense layerhaving a density higher than a density of the SiOCH film and a carbonconcentration higher than a carbon concentration of the SiOCH film;forming a hardmask layer on the dense layer; performing a plasma etchingon the dense layer and the SiOCH film by using the hardmask layer as amask to form a trench in the dense layer and the SiOCH film; andperforming wet etching on a surface of the trench formed in the SiOCHfilm, to remove a layer damaged by the plasma etching and processresidues.

According to a fourth aspect of the present invention, there is provideda semiconductor device comprising: an insulating film of a materialhaving a low relative dielectric constant; a SiOCH film formed on theinsulating film, having a carbon concentration higher than a carbonconcentration of the insulating film; a trench formed in the SiOCH filmand the insulating film; a first barrier layer formed on an insidesurface of the trench; a conductive layer filling the trench; and asecond barrier layer formed on the SiOCH film and the conductive layer.

According to a fifth aspect of the present invention, there is provideda semiconductor device comprising: a SiOCH film formed on an insulatingfilm; a dense layer formed on the SiOCH film, having a density higherthan a density of the SiOCH film and a carbon concentration higher thana carbon concentration of the SiOCH film; a trench formed in the denselayer and the SiOCH film; a first barrier layer formed on an insidesurface of the trench; a conductive layer filling the trench; and asecond barrier layer formed on the dense layer and the conductive layer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1A is a transmission electron microscope (TEM) photograph showing across section of a prototype of a semiconductor device in which metalhas been embedded in interconnect trenches; FIG. 1B is an enlarged viewof the TEM photograph of FIG. 1A; and FIG. 1C is a scanning electronmicroscope (SEM) photograph showing the CMP-planarized surface of thesemiconductor device after the embedment of the metal in theinterconnect trenches.

FIG. 2 is a diagram for explaining a method of manufacturing asemiconductor device according to the first embodiment of the presentinvention, showing a cross section of a structure in which an upperinterlayer insulating film is deposited after a lower interconnect layeris formed.

FIG. 3 is a diagram for explaining the method of manufacturing thesemiconductor device according to the first embodiment of the presentinvention, showing a cross section of a structure in which a SiOCH filmand a SiO₂ film are continuously formed to serve as a hardmask layer onthe interlayer insulating film.

FIG. 4 is a diagram for explaining the method of manufacturing thesemiconductor device according to the first embodiment of the presentinvention, showing a cross section of a structure in which aninterconnect trench pattern and a via pattern are formed in the upperinsulating film.

FIG. 5 is a diagram for explaining the method of manufacturing thesemiconductor device according to the first embodiment of the presentinvention, showing a cross section in which the interconnect trenchpattern and the via pattern are filled with a barrier metal and Cu.

FIG. 6 is a diagram for explaining the method of manufacturing thesemiconductor device according to the first embodiment of the presentinvention, showing a structure from which the hardmask layer containingthe SiOCH film and the SiO₂ film and an excess portion of the Cu filmare removed.

FIG. 7 is a TEM photograph showing a cross section of a structurefabricated with the method of manufacturing the semiconductor deviceaccording to the first embodiment of the present invention after theembedment of the interconnect metal.

FIG. 8 is a diagram of an electron energy loss spectroscopy (EELS)profile overlaying the TEM photograph of FIG. 7.

FIG. 9 is a diagram for explaining a method of manufacturing asemiconductor device according to a modified example of the firstembodiment of the present invention, showing a cross section of astructure in which the SiO₂ film, which is part of a hardmask layer, andan excess portion of a Cu film have been removed.

FIG. 10 is a diagram for explaining a method of manufacturing asemiconductor device according to the second embodiment of the presentinvention, showing a cross section of a structure in which a Cudiffusion barrier layer is deposited after the lower interconnect layeris formed.

FIG. 11 is a diagram for explaining the method of manufacturing thesemiconductor device according to the second embodiment of the presentinvention, showing a cross section of a structure in which an interlayerinsulating film and a hardmask layer are continuously formed on the Cudiffusion barrier layer.

FIG. 12 is a diagram for explaining the method of manufacturing thesemiconductor device according to the second embodiment of the presentinvention, showing a cross section of a structure in which aninterconnect trench pattern and a via pattern are formed in the upperinsulating film.

FIG. 13 is a diagram for explaining the method of manufacturing thesemiconductor device according to the second embodiment of the presentinvention, showing a cross section of a structure in which theinterconnect trench pattern and the via pattern are filled with abarrier metal and Cu.

FIG. 14 is a diagram for explaining the method of manufacturing thesemiconductor device according to the second embodiment of the presentinvention, showing a cross section of a structure from which thehardmask layer and an excess portion of the Cu film are removed.

FIG. 15 is a diagram for explaining the method of manufacturing thesemiconductor device according to the second embodiment of the presentinvention, showing a cross section of a structure in which an upperinterlayer insulating film is deposited and a dense layer is depositedon the surface of the film after the lower interconnect layer is formed.

FIG. 16 is a diagram for explaining the method of manufacturing thesemiconductor device according to the third embodiment of the presentinvention, showing a cross section of a structure in which a hardmasklayer is formed on interlayer insulating film.

FIG. 17 is a diagram for explaining the method of manufacturing thesemiconductor device according to the third embodiment of the presentinvention, showing a cross section of a structure in which aninterconnect trench pattern and a via pattern are formed in the upperinsulating film.

FIG. 18 is a diagram for explaining the method of manufacturing thesemiconductor device according to the third embodiment of the presentinvention, showing a cross section in which the interconnect trenchpattern and the via pattern are filled with a barrier metal and Cu.

FIG. 19 is a diagram for explaining the method of manufacturing thesemiconductor device according to the third embodiment of the presentinvention, showing a cross section of a structure from which thehardmask layer, the dense layer on the interlayer insulating film, andan excess portion of the Cu film are removed.

FIG. 20 is a diagram for explaining a modified example of the thirdembodiment of the present invention, showing a cross section of astructure from which a hardmask layer and an excess portion of a Cu filmare removed.

FIG. 21 is a diagram showing optical measurement results of a thicknessof the dense layer deposited on the interlayer insulating film with themethod of manufacturing the semiconductor device according to the thirdembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

According to the first to third embodiments of the present invention,the following three manufacturing methods, (1), (2) and (3), aresuggested as a means of preventing undercuts from being created beneathhardmask layer after the treatment of a low-k film.

(1) C-Concentration Gradient Hardmask Layer

The first embodiment suggests a method of depositing a hardmask layerformed of a SiO₂ film on a low-k film, in which a SiOCH film isdeposited as an initial film and then the concentration of carbon (C) isgradually reduced so that the SiO₂ film can be continuously formed. Byproviding the SiOCH as the initial film, damage to the low-k film can besuppressed.

(2) Single Deposition Process of Low-k Film to Hardmask Layer

The second embodiment suggests a method with which a low-k film isformed, and then the C concentration is gradually reduced so as tocontinuously form a hardmask layer of a SiO₂ film. The process of thelow-k film formation through the SiO₂ film (hardmask layer) depositionis performed in a single process, without shutting down the plasma.

(3) Formation of Dense Layer on Low-k Film

The third embodiment suggests a method of forming a dense layer having ahigh C concentration on the surface of the low-k film in order to reducethe plasma damage when depositing a hardmask layer on the low-k film.

According to the manufacturing methods (1) to (3), the low-k filmadopted for an interlayer insulating film in a semiconductor device issubjected to less damage during plasma etching for formation ofinterconnect trenches. Then, the creation of undercuts at the step ofremoval of a damaged layer is suppressed and the defects in embedment ofinterconnect metal is avoided.

The first to third embodiments of the present invention will beexplained below, with reference to the attached drawings.

Embodiment 1

FIGS. 2 to 6 are presented to explain a semiconductor device and amanufacturing method thereof according to the first embodiment of thepresent invention, showing cross sections of a structure at differentproduction steps in due order. The present embodiment focuses on afabrication process of a dual damascene structure; and therefore, theproduction of a device on a semiconductor substrate and the processafter the interconnect formation are omitted here.

First, as illustrated in FIG. 2, interconnect trenches are formed in asurface area of an insulating film (lower insulating film) 1 that isdeposited on a semiconductor substrate. After forming a Cu barrierlayer, if necessary, on an inside surface of the interconnect trenches,a Cu interconnect (conductive layer) 2 is embedded as a lowerinterconnect layer in the interconnect trenches. Thereafter, a Cudiffusion barrier layer (first insulating film) 3, such as a SiC film,is formed on the insulating film 1 and the Cu interconnect 2. This SiCfilm is used as an etching stopper and also for prevention of Cudiffusion. An upper insulating film (second insulating film) 4, such asa SiOCH film, is formed on the first insulating film 3. The SiOCH filmis a low-k film, having a relative dielectric constant of 3.0 or less.

Next, as indicated in FIG. 3, the SiOCH film 5 is formed immediatelyabove the second insulating film 4, and then a SiO₂ film 6 iscontinuously formed in such a manner as to have a carbon (C)concentration gradient by reducing the carbon concentration of the filminside a chamber in which plasma is being generated. The SiOCH film 5and the SiO₂ film 6 function together as a hardmask layer. For the gassource of this hardmask layer, an alkyl silane gas, for example, atleast any one of diethoxymethyl silane (DENS), octamethylcyclotetrasiloxane (OMCTS), tetramethyl cyclotetrasiloxane (TMCTS),trimethyl silane (TMS) and dimethyldimethoxy silane (DMDMOS) isincorporated.

In the continuous formation of the SiOCH film 5 and the SiO₂ film 6, theC concentration is reduced, for example, by gradually increasing theflow rate of oxygen in the reaction gas. More specifically, the flowrate is increased from 0 standard L/min (slm) to 1 slm in 3 seconds.

The SiOCH film 5 is provided in order to minimize damage to the secondinsulating film 4 when depositing the SiO₂ film thereon. If the SiO₂film is formed directly on the second insulating film 4, undercuts maybe created beneath the hardmask layer during a wet etching process whichis performed after the formation of the interconnect trenches, which maylead to lift-off of the hardmask layer.

Preferably, the thickness of the SiOCH film 5 is within a range of 1 to100 nm according to the current design rule. The etching rate of theSiO₂ film 6 in a hydrofluoric acid treatment should be 2 to 10 times ashigh as that of a thermally oxidized film.

Next, as illustrated in FIG. 4, a stacked film of the SiOCH film 5 andthe SiO₂ film 6 is patterned using the patterned stacked film as ahardmask, a plasma etching is performed on the second insulating film 4and the first insulating film 3 to form a via pattern 7. Then thestacked film of the SiOCH film 5 and the SiO₂ film 6 is patterned usingthe patterned stacked film as a hardmask, a plasma etching is performedon the second insulating film 4 to form an interconnect trench pattern8. Thereafter, a wet etching is performed on surfaces of inner walls ofthe via pattern 7 and the interconnect trench pattern 8 to remove adamage layer and process residues due to the plasma etching.

In the above example, the dual damascene structure, which does notrequire many production steps for fabrication, is described, but thetechnique can be applied to a single damascene structure, in which a viapattern and an interconnect trench are separately formed. The sameproduction steps for a conductive layer that is explained below are usedfor both structures.

As illustrated in FIG. 5, a Cu barrier layer 9 is formed on the SiO₂film 6 and also to cover the inside surfaces of the via pattern 7 andthe interconnect trench 8. Then, a Cu film 10 is deposited on the Cubarrier layer 9, for example, by electrolytic plating, so that Cu isfilled in the via pattern 7 and the interconnect trench portion 8.

Next, as indicated in FIG. 6, an excess portion of the Cu film 10, partof the Cu barrier layer 9, and all of the SiO₂ film 6 and the SiOCH film5 are removed by CMP. Thereafter, a third insulating film 11 is formedon the second insulating film 4 and the Cu film 10.

The third insulating film 11 is formed of the same material as the firstinsulating film 3 such as SiC, to serve as an etching stopper and toprevent Cu from diffusing.

Preferably, the thickness of the SiOCH film 5 should be less than thatof the SiO₂ film 6 because the CMP planarization characteristic of theSiOCH film 5 is not as good as that of the SiO₂ film 6. For example,when the total thickness of the SiO₂ film 6 and the SiOCH film 5 is 60nm, the thickness of the SiOCH film 5 should be less than 30 nm. If theSiOCH film 5 is thicker than the SiO₂ film 6, the interconnectresistance may widely vary.

FIG. 7 shows a cross-section TEM image before the CMP, while FIG. 8shows EELS analysis results before the CMP. FIG. 7 is a cross-sectionTEM photograph of the structure fabricated with the semiconductor devicemanufacturing method according to the first embodiment, after theembedment of the interconnect metal. In FIG. 8, an EELS profile isoverlaid with the cross-section TEM photograph of FIG. 7 after theembedment of the interconnect metal. As can be seen from the drawings,the thickness of the SiOCH film 5 is approximately 5 nm so as to bethinner than the SiO₂ film 6. From the EELS analysis results, the Cconcentration gradient region is approximately 5 nm. The structure is ingood condition, free of undercuts as the ones formed beneath thehardmask layer illustrated in FIGS. 1A to 1C.

According to such structure and manufacturing method, in a semiconductordevice adopting a low-k film for an interlayer insulating film, damageto the low-k film can be reduced during the formation of theinterconnect trenches, and formation of undercuts can be suppressed.Defects in embedment of interconnect metal can be thereby reduced.

FIG. 9 is presented to explain a modified example of the semiconductordevice manufacturing method according to the first embodiment of thepresent invention, showing a cross section of a structure after theremoval of the SiO₂ film as part of the hardmask layer and an excessportion of the Cu film. Unlike the structure of FIG. 6, the SiOCH film 5remains after the CMP in the structure of the modified exampleillustrated in FIG. 9. After the CMP, a third insulating film 11 isformed of SiC or the like on this SiOCH film 5 to serve as an etchingstopper and to prevent Cu from diffusing.

After the third insulating film 11 is formed, the steps of FIGS. 2through 6 are repeated as required so as to achieve multilayeredinterconnects.

By leaving the SiOCH film 5 on the second insulating film 4, the secondinsulating film 4 would not be exposed to an atmosphere of plasma whenreducing oxides on the Cu interconnect so that an inter-interconnecttime dependent dielectric breakdown (TDDB) strength is prevented frombeing reduced. In other words, the value k of the SiOCH film 5 is sethigher than that of the second insulating film 4. The second insulatingfilm 4 is thereby prevented from being exposed to the plasma atmosphere,for example, in a NH₃ plasma treatment that is generally conducted toreduce oxides on the Cu interconnect before the formation of the thirdinsulating film 11. A methyl group near the surface of the secondinsulating film 4 can be thereby prevented from being detached, andcreation of a damaged layer can be avoided. As a result, resistanceproperties to the plasma treatment can be improved, and theinter-interconnect TDDB strength can be maintained.

It should be noted; however, that the SiOCH film 5 would increase theinter-interconnect capacitance, and thus the structure of FIG. 6 or 9should be selected in accordance with the specs required for a device.

Embodiment 2

FIGS. 10 to 14 are provided to explain a semiconductor device and amanufacturing method thereof according to the second embodiment of thepresent invention, showing cross sections obtained at differentproduction steps in due order. In a similar manner to the firstembodiment, fabrication of a dual damascene structure is focused on inthe present embodiment, and thus the formation process of a device onthe semiconductor substrate and the process after the formation ofinterconnects are omitted here.

First, interconnect trenches are formed in a surface area of aninsulating film (lower insulating film) 1 that is provided on asemiconductor substrate, as indicated in FIG. 10. After forming a Cubarrier layer, if necessary, in an inside surface of interconnecttrenches, a Cu interconnect 2 (conductive layer) is embedded in theinterconnect trench and formed as a lower interconnect layer.Thereafter, a SiC film or the like is deposited as a Cu diffusionbarrier layer (first insulating film) 3 on the insulating film 1 and theCu interconnect 2.

Next, as illustrated in FIG. 11, a SiOCH film 12 or the like is formedas an upper insulating layer (second insulating film) on the firstinsulating film 3, and then the C concentration of the film is graduallyreduced in a chamber in which plasma is being generated so that a SiO₂film 13 is continuously formed to serve as a hardmask layer. Thecontinuous formation of the SiOCH film 12 and the SiO₂ film 13 is thesame as the formation of the C-concentration gradient hardmask layeraccording to the first embodiment. For example, a flow rate of oxygen inthe reaction gas is gradually increased to reduce the C concentration.More specifically, in the same manner as in the first embodiment, theflow rate is increased from 0 standard L/min (slm) to 1 slm in 3seconds.

As discussed above, damage to the second insulating film 12 can bereduced when forming the SiO₂ film 13 as the hardmask layer, bycontinuously forming the second insulating film 12 and the SiO₂ film 13.

The steps of FIGS. 12, 13 and 14 that follow the above process are thesame as those of FIGS. 4, 5 and 6, and thus detailed explanations areomitted here.

According to the above structure and manufacturing method of asemiconductor device adopting a low-k film for an interlayer insulatingfilm, damage to the low-k film can be minimized in the formation of theinterconnect trenches so that creation of undercuts can be suppressedand defects in embedment of interconnect metal can be reduced.

Embodiment 3

FIGS. 15 to 20 are provided to explain a semiconductor device and amanufacturing method thereof according to the third embodiment of thepresent invention, showing cross sections obtained at different steps ofthe production in due order. Similarly to the first and secondembodiments, the present embodiment focuses on the fabrication of a dualdamascene structure; and therefore, the formation process of a device ona semiconductor substrate and the process after the formation ofinterconnects are omitted here.

First, as illustrated in FIG. 15, interconnect trenches are formed in asurface area of an insulating film (lower insulating film) 1 that isdeposited on the semiconductor substrate. After forming a Cu barrierlayer, if necessary, on an inside surface of interconnect trenches, a Cuinterconnect (conductive layer) 2 is embedded in the interconnecttrenches to form a lower interconnect layer. Thereafter, a SiC film orthe like is formed on an insulating film 1 and the Cu interconnect 2, asa Cu diffusion barrier layer (first insulating film) 3. Next, a SiOCHfilm or the like is formed on a first insulating film 3 as an upperinsulating film (second insulating film) 14, and then a SiOCH film(dense layer) 15 is continuously formed by gradually reducing the amountof porogen in the film inside a plasma generating chamber. The completedSiOCH film 15 does not contain any porogen.

Thereafter, the porogen is removed from the SiOCH film 14 by a curingprocess so as to obtain a porous film. Because porogen is not includedin the SiOCH film 15 during the curing process, this film has a higherdensity than the SiOCH film 14. For this reason, the value k of theSiOCH film 15 is greater than that of the SiOCH film 14, which improvesthe damage resistance to the plasma. In addition, the SiOCH film 15 hasa higher carbon concentration than the SiOCH film 14.

Next, as indicated in FIG. 16, a SiO₂ film is deposited on the SiOCHfilm 15 to form a hardmask layer 16.

As mentioned above, the SiOCH film 15 having a high density is providedbetween the SiOCH film 14 and the SiO₂ film 16 so that damage to theSiOCH film 14 can be suppressed. Furthermore, with a dense layercovering the surface of the structure, adhesion to the upper layer (SiClayer) is improved, offering structural stability.

The density of the SiOCH film 14 is approximately 1.1 g/cc when thevalue k is 2.5. The SiOCH film 15 having the value k within the range of2.7 to 3.0 is formed continuously on the SiOCH film 14. The density ofthe SiOCH film 15 is set to 1.3 to 1.4 g/cc.

The steps of FIGS. 17 to 20 that follow the above process areessentially the same as those of FIGS. 4 to 6 and 9; and therefore, thedetailed explanations are omitted here.

FIG. 21 shows optical thickness measurement results of the dense layer(SiOCH film 15) that is deposited on the SiOCH film 14 with thesemiconductor device manufacturing method according to the thirdembodiment of the present invention. This confirms the formation of theSiOCH film 15 having an average thickness of 10 nm.

According to the above structure and manufacturing method of asemiconductor device adopting a low-k film for an interlayer insulatingfilm, damage to the low-k film is minimized during the formation ofinterconnect trenches, and formation of undercuts is suppressed so thatdefects in embedment of interconnect metal can be reduced.

As discussed above, with the semiconductor device and the manufacturingmethod thereof according to the first to third embodiments of thepresent invention, a semiconductor device incorporating an interlayerinsulating film of a low relative dielectric constant can be offered, inwhich damage to the interlayer insulating film is reduced during theplasma treatment, and formation of undercuts is suppressed at removal ofthe damaged layer.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-16. (canceled)
 17. A semiconductor device comprising: an insulatingfilm of a material having a low relative dielectric constant; an SiOCHfilm formed on the insulating film, having a carbon concentration higherthan a carbon concentration of the insulating film; a trench formed inthe SiOCH film and the insulating film; a first barrier layer formed onan inside surface of the trench; a conductive layer filling the trench;and a second barrier layer formed on the SiOCH film and the conductivelayer.
 18. The device according to claim 17, wherein a relativedielectric constant of the insulating film is less than or equal to 3.0.19. The device according to claim 17, wherein the insulating film isformed of SiOCH.
 20. A semiconductor device comprising: an SiOCH filmformed on an insulating film; a dense layer formed on the SiOCH film,having a density higher than a density of the SiOCH film and a carbonconcentration higher than a carbon concentration of the SiOCH film; atrench formed in the dense layer and the SiOCH film; a first barrierlayer formed on an inside surface of the trench; a conductive layerfilling the trench; and a second barrier layer formed on the dense layerand the conductive layer.